MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller
authorQuentin Schulz <quentin.schulz@bootlin.com>
Wed, 25 Jul 2018 12:26:20 +0000 (14:26 +0200)
committerPaul Burton <paul.burton@mips.com>
Mon, 30 Jul 2018 17:34:28 +0000 (10:34 -0700)
commit6386889ac23e2c1c8276a111765421577539dd7a
treee7c7fe235e3e8b8a4c54d3e505e99189a6b6b830
parent0211d49e5200554eb836c9a12a247d4c11fe571c
MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller

The GPIO controller also serves as an interrupt controller for events
on the GPIO it handles.

An interrupt occurs whenever a GPIO line has changed.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20015/
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
arch/mips/boot/dts/mscc/ocelot.dtsi