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(parent: 262baa4) | patch
[AMDGPU] support image load/store a16
authorNeil Henning <neil.henning@amd.com>
Wed, 31 Oct 2018 10:34:48 +0000 (10:34 +0000)
committerNeil Henning <neil.henning@amd.com>
Wed, 31 Oct 2018 10:34:48 +0000 (10:34 +0000)
commit63718b214aff93535f2c349db367f6165bb67e9c
tree96a26ad3a7cf5860a1065a355700cdece0fd901ftree | snapshot
parent262baa4753e22ef25906a2fcea6e7e0d7140d9f2commit | diff
[AMDGPU] support image load/store a16

Our a16 support was only enabled for sample/gather and buffer
load/store, but not for image load/store operations (which take an i16
as the pixel index rather than a half).

Fix our isel lowering and add test cases to prove it out.

Differential Revision: https://reviews.llvm.org/D53750

llvm-svn: 345710
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll [new file with mode: 0644] blob
llvm/test/MC/AMDGPU/mimg.s diff | blob | history
Domain: System / Toolchain;