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(parent: eb72e2b) | patch
upstream: [media] mt9p031: Add support for PLL bypass
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Sun, 9 Feb 2014 20:31:47 +0000 (17:31 -0300)
committerChanho Park <chanho61.park@samsung.com>
Thu, 7 Aug 2014 05:26:55 +0000 (14:26 +0900)
commit6368a989cc4a8810bdccac3f1c7ebe91d68901c6
treeacc8a37f2cc29428d99ea147d755f1e51d5b314ftree | snapshot
parenteb72e2b62ce19e539ff5da3f1cac79fb5899dcf4commit | diff
upstream: [media] mt9p031: Add support for PLL bypass

When the input clock frequency is out of bounds for the PLL, bypass the
PLL and just divide the input clock to achieve the requested output
frequency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
drivers/media/i2c/mt9p031.c diff | blob | history
Domain: System / Kernel;