[X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel...
authorCraig Topper <craig.topper@intel.com>
Wed, 11 Sep 2019 23:54:36 +0000 (23:54 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 11 Sep 2019 23:54:36 +0000 (23:54 +0000)
commit635d383fad2baef4cb4b241c8dd31c91913c0f32
tree6b4dc58b7030432c7a9cd58db71dbde494c8de65
parent55d86f04c737a9f9791500d5758af17e73558229
[X86] Enable -mprefer-vector-width=256 by default for Skylake-avx512 and later Intel CPUs.

AVX512 instructions can cause a frequency drop on these CPUs. This
can negate the performance gains from using wider vectors. Enabling
prefer-vector-width=256 will prevent generation of zmm registers
unless explicit 512 bit operations are used in the original source
code.

I believe gcc and icc both do something similar to this by default.

Differential Revision: https://reviews.llvm.org/D67259

llvm-svn: 371694
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Target/X86/X86.td
llvm/test/CodeGen/X86/min-legal-vector-width.ll