powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMs
authorYork Sun <yorksun@freescale.com>
Thu, 17 Mar 2011 18:18:11 +0000 (11:18 -0700)
committerKumar Gala <galak@kernel.crashing.org>
Thu, 24 Mar 2011 14:20:50 +0000 (09:20 -0500)
commit634bc5542959f9ab53961642a1106c4acd2757f3
treea6a80bb5340c08542198d613d5588651dce216eb
parent08b3f7599f7bdf7e96cf46ecb9eecffc92b323d2
powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMs

Tested all possible values for clk_adjust and write_data_delay for dual
rank UDIMM and RDIMM to revise the tables.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/freescale/mpc8572ds/ddr.c