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[RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac instructions
authorShihPo Hung <shihpo.hung@sifive.com>
Tue, 22 Dec 2020 13:30:24 +0000 (05:30 -0800)
committerShihPo Hung <shihpo.hung@sifive.com>
Wed, 23 Dec 2020 08:42:04 +0000 (00:42 -0800)
commit6301871d06d6ea0195b5ea3b53288dcfe229557a
treef0e5537d83bfad45e8d5d8702a184a735bd8226ftree | snapshot
parentbdef1f87aba656a64b34f76d2a6613b6e9299a03commit | diff
[RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac instructions

This patch defines vfwmacc, vfwnmacc, vfwmsc, vfwnmsac intrinsics
and lower to V instructions.
We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Differential Revision: https://reviews.llvm.org/D93693
llvm/include/llvm/IR/IntrinsicsRISCV.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll [new file with mode: 0644] blob
Domain: System / Toolchain;