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(parent: 22c42b0) | patch
drm/amd/display: fix dcn315 memory channel count and width read
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tue, 30 Aug 2022 19:16:40 +0000 (15:16 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 19 Sep 2022 19:09:44 +0000 (15:09 -0400)
commit62f0576c42993a442ae722fe2e67a140e4669945
tree9323fb825098b2a333bc7de67b7fe72c71668827tree | snapshot
parent22c42b0ec225c92db33e4b3045ad15baf1427cffcommit | diff
drm/amd/display: fix dcn315 memory channel count and width read

[Why & How]
Correctly set ddr5 channel width to 8 bytes

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c diff | blob | history
Domain: System / Kernel;