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(parent: 91405eb) | patch
MIPS: introduce CPU_R4K_CACHE_TLB
authorFlorian Fainelli <florian@openwrt.org>
Tue, 31 Jan 2012 17:18:45 +0000 (18:18 +0100)
committerJohn Crispin <blogic@openwrt.org>
Wed, 22 Aug 2012 21:46:38 +0000 (23:46 +0200)
commit62cedc4fde2d15b08e4502aa3fb2d9d798f3ccd8
treefee5a50adcb7181d44bf4f3364d46883bc49dd35tree | snapshot
parent91405eb69ee007ee854aa917e2a15e6ccede2cd1commit | diff
MIPS: introduce CPU_R4K_CACHE_TLB

R4K-style CPUs having common code to support their caches and tlb have this
boolean defined by default. Allows us to remove some lines in
arch/mips/mm/Makefile.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/3328/
Signed-off-by: John Crispin <blogic@openwrt.org>
arch/mips/Kconfig diff | blob | history
arch/mips/mm/Makefile diff | blob | history
Domain: System / Kernel;