author | Hsiangkai Wang <kai.wang@sifive.com> | |
Sat, 19 Dec 2020 13:46:29 +0000 (21:46 +0800) | ||
committer | Hsiangkai Wang <kai.wang@sifive.com> | |
Sun, 20 Dec 2020 09:38:57 +0000 (17:38 +0800) | ||
commit | 62c94f06781dba1a3ec717c1486934de2e939052 | |
tree | 29f197c1e915f35dcd6ae9240eacd810613a4233 | tree | snapshot |
parent | 37974b493a48cf97ac3d486512d6cd70c176924a | commit | diff |
llvm/include/llvm/IR/IntrinsicsRISCV.td | diff | blob | history | |
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | diff | blob | history | |
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll | [new file with mode: 0644] | blob |