GlobalISel: implement low-level type with just size & vector lanes.
authorTim Northover <tnorthover@apple.com>
Wed, 20 Jul 2016 19:09:30 +0000 (19:09 +0000)
committerTim Northover <tnorthover@apple.com>
Wed, 20 Jul 2016 19:09:30 +0000 (19:09 +0000)
commit62ae568bbb9c4d22d341a71d12ab0bc74506476c
tree3f97084359b5198bb5223ea2c93d9b01cc608be0
parent228d27c70f4ba3f32f07719c9a299fd7d7db2d5b
GlobalISel: implement low-level type with just size & vector lanes.

This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

llvm-svn: 276158
21 files changed:
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/include/llvm/CodeGen/LowLevelType.h [new file with mode: 0644]
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/CMakeLists.txt
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/lib/CodeGen/LowLevelType.cpp [new file with mode: 0644]
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/CodeGen/MIRParser/MILexer.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
llvm/test/CodeGen/MIR/X86/generic-instr-type-error.mir
llvm/test/CodeGen/MIR/X86/generic-virtual-registers.mir