include: Remove sideleg and sedeleg
authorRahul Pathak <rpathak@ventanamicro.com>
Wed, 24 Aug 2022 14:54:37 +0000 (20:24 +0530)
committerAnup Patel <anup@brainfault.org>
Thu, 1 Sep 2022 10:07:22 +0000 (15:37 +0530)
commit622cc5f014eb983348aa0dc7fb5fbde43d074782
tree4cc84a48953e0f6f5e02b2a33e446d9a6287a576
parentcbaa9b0333517b3c25bea8d1c71ac8005ff1f727
include: Remove sideleg and sedeleg

sideleg and sedeleg csrs are not part of riscv isa spec
anymore, these csrs were part of N extension which
is removed from the riscv isa specification.

These commits removed all traces of these csrs from
riscv spec (https://github.com/riscv/riscv-isa-manual) -

commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)")
commit b6cade07034d ("Remove N extension chapter for now")

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
include/sbi/riscv_encoding.h