projects / platform / kernel / linux-exynos.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 57520bc) | patch
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain
authorDamien Lespiau <damien.lespiau@intel.com>
Thu, 30 Apr 2015 15:39:20 +0000 (16:39 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 May 2015 11:03:35 +0000 (13:03 +0200)
commit6222709d60734dd1e11f8d24520d9f23b4eb953e
treedea715d2e0caeb6960df4622064f3e9926a21ef5tree | snapshot
parent57520bc55cf56b77e7a67cb0877fafdb65181f6acommit | diff
drm/i915/skl: Make the Misc I/O power well part of the PLLS domain

The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
the PLLS power domain to ensure those two power wells are up.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_runtime_pm.c diff | blob | history
Domain: System / Kernel;