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(parent: 7c001e5) | patch
xtensa: add missing isync to the cpu_reset TLB code
authorMax Filippov <jcmvbkbc@gmail.com>
Mon, 12 Aug 2019 22:01:30 +0000 (15:01 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 25 Aug 2019 08:47:47 +0000 (10:47 +0200)
commit61f6ecb758453d51f25c4cd991cfcc52c41e709a
tree85cb51ec72802fbbc62a41d309e5b86d6209ddadtree | snapshot
parent7c001e5aab6dcf4883d67fe3154ce73725251f47commit | diff
xtensa: add missing isync to the cpu_reset TLB code

commit cd8869f4cb257f22b89495ca40f5281e58ba359c upstream.

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/xtensa/kernel/setup.c diff | blob | history
Domain: System / Kernel;