[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 10 Mar 2016 20:40:26 +0000 (20:40 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 10 Mar 2016 20:40:26 +0000 (20:40 +0000)
commit61eb49e437d7a35d3f7e7146391804553e2ade2e
treedc176c05b488ab3976ec216435ffa348de38868e
parent3c8fc57e16839194b4eb569b6fb35eda03249aeb
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG

Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns.

Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion).

Differential Revision: http://reviews.llvm.org/D17691

llvm-svn: 263159
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/pr26870.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/vec_int_to_fp.ll
llvm/test/CodeGen/X86/vector-zext.ll