RISC-V: Print SSTC in canonical order
authorPalmer Dabbelt <palmer@rivosinc.com>
Tue, 20 Sep 2022 20:45:18 +0000 (13:45 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 7 Oct 2022 03:03:27 +0000 (20:03 -0700)
commit61a41d16ad20657f93613229a8b17766c51dc849
tree08fed1a62ce0316760d57a4f944e7ba14be3eb59
parent542d353e25520e7db11d2cdb31d19c50ed921812
RISC-V: Print SSTC in canonical order

This got out of order during a merge conflict, fix it by putting the
entries in the correct order.

Fixes: 7ab52f75a9cf ("RISC-V: Add Sstc extension support")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20220920204518.10988-1-palmer@rivosinc.com/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/kernel/cpu.c