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ARM: dts: bcm2711: Add the missing L1/L2 cache information
authorRichard Schleich <rs@noreya.tech>
Tue, 21 Dec 2021 22:48:30 +0000 (23:48 +0100)
committerFlorian Fainelli <f.fainelli@gmail.com>
Fri, 11 Feb 2022 22:23:38 +0000 (14:23 -0800)
commit618682b350990f8f1bee718949c4b3858711eb58
treece7dcebec69c9ac702afbab131e7f44459260333tree | snapshot
parentbdf8762da268d2a34abf517c36528413906e9cd5commit | diff
ARM: dts: bcm2711: Add the missing L1/L2 cache information

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2711 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
arch/arm/boot/dts/bcm2711.dtsi diff | blob | history
Domain: System / Kernel;