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(parent: a097a5e) | patch
clk: starfive: Add StarFive JH7110 PLL clock driver
authorXingyu Wu <xingyu.wu@starfivetech.com>
Mon, 17 Jul 2023 02:30:37 +0000 (10:30 +0800)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 19 Jul 2023 17:08:00 +0000 (18:08 +0100)
commit616bc1dea1ac8909dfcd6d32802df6fe50eddde8
treed39b3b35a2179eb315f5597b563f31e13d34d252tree | snapshot
parenta097a5ec14dff59568b1e6c8bd8cc37a21d8811fcommit | diff
clk: starfive: Add StarFive JH7110 PLL clock driver

Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.

Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
MAINTAINERS diff | blob | history
drivers/clk/starfive/Kconfig diff | blob | history
drivers/clk/starfive/Makefile diff | blob | history
drivers/clk/starfive/clk-starfive-jh7110-pll.c [new file with mode: 0644] blob
Domain: System / Kernel;