phy: ralink: phy-mt7621-pci: use kernel clock APIS
authorSergio Paracuellos <sergio.paracuellos@gmail.com>
Sat, 8 May 2021 07:09:27 +0000 (09:09 +0200)
committerVinod Koul <vkoul@kernel.org>
Fri, 14 May 2021 10:46:28 +0000 (16:16 +0530)
commit60ece833ccd00c4fc9b10bbce2fa6291f61c6230
treefd0eb39e609f73f26323e07f5d0dac563132f9e0
parent77945a345acfc32b8c1aadf470b55d6a4aa8e01e
phy: ralink: phy-mt7621-pci: use kernel clock APIS

MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
This allow us to properly use kernel clock apis to get
the clock frequency needed for the phy configuration
instead of use custom architecture code to do the same.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210508070930.5290-4-sergio.paracuellos@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/ralink/phy-mt7621-pci.c