RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

Use Zbs when generating a sequence for
   "if ((a & twobits) == singlebit) ..."
that can be expressed as
   bexti + bexti + andn.

gcc/ChangeLog:

	* config/riscv/bitmanip.md
	(*branch<X:mode>_mask_twobits_equals_singlebit):
	Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C
	has one	of these tow bits set.
	* config/riscv/predicates.md (const_twobits_not_arith_operand):
	New predicate.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-if_then_else-01.c: New test.