perf/x86: Implement PERF_SAMPLE_BRANCH for Intel CPUs
authorStephane Eranian <eranian@google.com>
Thu, 9 Feb 2012 22:20:57 +0000 (23:20 +0100)
committerIngo Molnar <mingo@elte.hu>
Mon, 5 Mar 2012 13:55:41 +0000 (14:55 +0100)
commit60ce0fbd072695866cb27b729690ab59dce705a5
treee11c2aa50129bbcbc4e9eb39bf00bbfd63891df3
parent88c9a65e13f393fd60d8b9e9c659a34f9e39967d
perf/x86: Implement PERF_SAMPLE_BRANCH for Intel CPUs

This patch implements PERF_SAMPLE_BRANCH support for Intel
x86processors. It connects PERF_SAMPLE_BRANCH to the actual LBR.

The patch adds the hooks in the PMU irq handler to save the LBR
on counter overflow for both regular and PEBS modes.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1328826068-11713-8-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event.h
arch/x86/kernel/cpu/perf_event_intel.c
arch/x86/kernel/cpu/perf_event_intel_ds.c
arch/x86/kernel/cpu/perf_event_intel_lbr.c