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(parent: 9bd338f) | patch
GBE: fix baytrail L3 cache configuration.
authorZhigang Gong <zhigang.gong@linux.intel.com>
Tue, 27 May 2014 08:58:28 +0000 (16:58 +0800)
committerZhigang Gong <zhigang.gong@intel.com>
Wed, 28 May 2014 01:08:24 +0000 (09:08 +0800)
commit604c0ee37c031a902f28a3a181e1314c8bab46f3
tree6bd570090e9c76bc65139026dad9ff8a4d3d995atree | snapshot
parent9bd338fcc191fbc364f5cc1d4b2e1cbd645959a3commit | diff
GBE: fix baytrail L3 cache configuration.

Reduce URB from 128KB to 64KB causes rendering artifact in X window.
I have to change it to 96KB URB and also change the RO and DC to 16KB
to satisfy the total 192KB L3 size limitation.

With this fix, the artifact is gone and utests has no new failures.

Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-by: Guo Yejun <yejun.guo@intel.com>
src/intel/intel_gpgpu.c diff | blob | history
Domain: SCM / Uncategorized;