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author	Nikita Popov <npopov@redhat.com>
	Thu, 5 Jan 2023 12:13:06 +0000 (13:13 +0100)
committer	Nikita Popov <npopov@redhat.com>
	Thu, 5 Jan 2023 12:21:20 +0000 (13:21 +0100)
commit	60442f0d442723a487528bdd8b48b24657a025e8
tree	977510b3cf6c3c669aa3f148adca01df2754b5af	tree \| snapshot
parent	c820f2a43eaba02db97c4ff60c58a58e6bdd391d	commit \| diff

[CodeGen] Convert some tests to opaque pointers (NFC)

These are mostly MIR tests, which I did not handle during previous
conversions.

323 files changed:

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-block-addr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-invalid-addrspace.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/memory-legalizer-region.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-load-store-agpr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/merge-out-of-order-ldst.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/phi-elimination-end-cf.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-ilp.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/waitcnt.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/codesize-ifcvt.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/const-load-align-thumb.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/dbg-range-extension.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/fp16-litpool-arm.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/machine-sink-multidef.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/noreturn-csr-skip.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/pei-swiftself.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/single-issue-r52.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/stack_frame_offset.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/store-prepostinc.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/vldm-liveness.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/vldmia-sched.mir		diff \| blob \| history
llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/addrmode-immop.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/addrmode-no-rdef.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/bank-conflict-load.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/bank-conflict.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/cext-opt-negative-fi.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/cext-opt-stack-no-rr.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/cext-unnamed-global.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/early-if-conv-lifetime.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/early-if-predicator.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/hwloop-dbg-register.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir		diff \| blob \| history
llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/add_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/brindirect.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fabs_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fence.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/floating_point_vec_arithmetic_operations.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/gloal_address.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_4_unaligned_r6.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/load_store_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/mul_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/pointers.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/rem_and_div_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/store_4_unaligned_r6.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/sub_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/truncStore_and_aExtLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/instruction-select/zextLoad_and_sextLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/brindirect.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fabs_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fence.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/floating_point_vec_arithmetic_operations_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/load_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub_vec_builtin.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/truncStore_and_aExtLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/zextLoad_and_sextLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/TypeInfoforMF_skipCopies.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/add_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/brindirect.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fabs_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fence.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/floating_point_vec_arithmetic_operations.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/global_address.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load_store_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/mul_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/phi.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/pointers.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/rem_and_div_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store_4_unaligned.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/sub_vec.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/test_TypeInfoforMF.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/truncStore_and_aExtLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/GlobalISel/regbankselect/zextLoad_and_sextLoad.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/compactbranches/compact-branch-implicit-def.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/micromips-eva.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-lwp-swp.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/micromips-sizereduction/micromips-no-lwp-swp.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir		diff \| blob \| history
llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/block-placement-1.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/livevars-crash1.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/livevars-crash2.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/phi-eliminate.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/remove-redundant-li-skip-imp-kill.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/schedule-addi-load.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/sext_elimination.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/shrink-wrap.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir		diff \| blob \| history
llvm/test/CodeGen/PowerPC/two-address-crash.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cmplx_cong.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir		diff \| blob \| history
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-write.mir		diff \| blob \| history
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-negative-offset.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-killed.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-pred.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/bti-const-island.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/frame-index-addrmode-t2i8s4.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/high-reg-spill.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/ifcvt-dead-predicate.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-tp-loop.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-wls-block-placement.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/phi_prevent_copy.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/postinc-distribute.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/store-prepostinc.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir		diff \| blob \| history
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llvm/test/CodeGen/Thumb2/swp-regpressure.mir		diff \| blob \| history
llvm/test/CodeGen/Thumb2/tbb-removeadd.mir		diff \| blob \| history
llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.mir		diff \| blob \| history
llvm/test/CodeGen/WebAssembly/exception.mir		diff \| blob \| history
llvm/test/CodeGen/WebAssembly/function-info.mir		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/legalize-ptr-add.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir		diff \| blob \| history
llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir		diff \| blob \| history
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