RISC-V: Fix testsuite regression due to recent IRA changes.
authorKito Cheng <kito.cheng@sifive.com>
Wed, 11 Mar 2020 09:48:10 +0000 (17:48 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 11 Mar 2020 16:57:19 +0000 (00:57 +0800)
commit5fea87cc7902c7c03c0d3c8cf7784cd99db8315d
tree57fd1d3b69a148a205eeb4a8a838492e9b36547f
parentcb99630f254aaec6591e0a200b79905b31d24eb3
RISC-V: Fix testsuite regression due to recent IRA changes.

After IRA changes, atomic version will use one more register, but
non-atomic still use 2 registers, however this testcase isn't testing for
atomic feature, so I decide change the testcase to always use COUNT++
to test.

ChangeLog

gcc/testsuite/

Kito Cheng  <kito.cheng@sifive.com>

* gcc.target/riscv/interrupt-2.c: Update testcase and expected output.
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/riscv/interrupt-2.c