review.tizen.org Git - platform/upstream/tvm.git/commit

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author	Luis Vega <vegaluisjose@users.noreply.github.com>
	Wed, 4 Sep 2019 05:19:01 +0000 (22:19 -0700)
committer	Thierry Moreau <moreau@uw.edu>
	Wed, 4 Sep 2019 05:19:01 +0000 (22:19 -0700)
commit	5fe61fd1b4357dfa111a165d8a0367aca9132b7b
tree	28e0b15fcbb3e072a91b4b75b7cedb6a1c29aa48	tree \| snapshot
parent	f4a28c4bc53589c3b985a3b967519e808bcda3c7	commit \| diff

[VTA][Chisel] add scalafmt and format existing scala codebase (#3880)

* [VTA][Chisel] add scalafmt and format existing scala codebase

* change column width to 100

* add scalafmt conf file as a valid file type

* add asf header to scalafmt conf file and rerun formatter

39 files changed:

tests/lint/check_file_type.py		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/.scalafmt.conf	[new file with mode: 0644]	blob
vta/apps/tsim_example/hardware/chisel/Makefile		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/project/plugins.sbt		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Accel.scala		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/Compute.scala		diff \| blob \| history
vta/apps/tsim_example/hardware/chisel/src/main/scala/accel/RegFile.scala		diff \| blob \| history
vta/hardware/chisel/.scalafmt.conf	[new file with mode: 0644]	blob
vta/hardware/chisel/Makefile		diff \| blob \| history
vta/hardware/chisel/project/plugins.sbt		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Compute.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Configs.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Core.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Decode.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/EventCounters.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Fetch.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/ISA.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Load.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/LoadUop.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Semaphore.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/Store.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/TensorAlu.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/TensorGemm.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/TensorLoad.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/TensorStore.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/core/TensorUtil.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/dpi/VTAHostDPI.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/dpi/VTAMemDPI.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/interface/axi/AXI.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/Configs.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/IntelShell.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/SimShell.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/VCR.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/VME.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/VTAShell.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/shell/XilinxShell.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/util/Config.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/util/GenericParameterizedBundle.scala		diff \| blob \| history
vta/hardware/chisel/src/main/scala/vta/Configs.scala		diff \| blob \| history

Domain: Machine Learning / ML Framework;

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