net: hns3: refactor interrupt coalescing init function
authorFuyun Liang <liangfuyun1@huawei.com>
Fri, 12 Jan 2018 08:23:11 +0000 (16:23 +0800)
committerDavid S. Miller <davem@davemloft.net>
Fri, 12 Jan 2018 15:12:32 +0000 (10:12 -0500)
commit5fd4789a98f8661a0e8db3daf21b774213c99487
treeb65c880409525fb03ce8a38cdda92b5de207b4a2
parent434776a5fae2633ab524eb7dceb4d105c40852bb
net: hns3: refactor interrupt coalescing init function

In the hardware, the coalesce configurable registers include GL0, GL1,
GL2. In the driver, the TX queues use the register GL1 and the RX queues
use the register GL0. This function initializes the configuration of the
interrupt coalescing, but does not distinguish between the TX direction
and the RX direction. It will cause some confusion.

This patch refactors the function to initialize the TX GL and the RX GL
separately. And the initialization of related variables also is added to
this patch.

Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c