projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 12607f5) | patch
[RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy...
authorYeting Kuo <yeting.kuo@sifive.com>
Mon, 5 Sep 2022 13:57:22 +0000 (21:57 +0800)
committerYeting Kuo <yeting.kuo@sifive.com>
Tue, 13 Sep 2022 02:09:49 +0000 (10:09 +0800)
commit5fcb5d77599e2b028dd8b7b8a3a7853701838e0c
tree82e969ee573a7785ce2397faae210ac64d243034tree | snapshot
parent12607f57da9aa990eb9ec3f671214058d86ab1b1commit | diff
[RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy operand.

The original code may have incorrect result if there is a masked instruction
without policy operand to make us set its policy to TUMU. The patch adds an
assertion to catch the instruction.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D133302
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
Domain: System / Toolchain;