clk: samsung: exynos4: Register PLL rate tables for Exynos4210
authorTomasz Figa <t.figa@samsung.com>
Mon, 26 Aug 2013 17:09:09 +0000 (19:09 +0200)
committerMike Turquette <mturquette@linaro.org>
Fri, 6 Sep 2013 20:33:57 +0000 (13:33 -0700)
commit5fadfc7ed37efe272983639f0d2f8c801303e796
tree351d9e5309abb26879efb82c4e8da1c56e7ecb47
parent4f7641f588dcc5f614a2dae18e614da7abd13604
clk: samsung: exynos4: Register PLL rate tables for Exynos4210

This patch adds rate tables for PLLs that can be reconfigured at runtime
for Exynos4210 SoCs. Provided tables contain PLL coefficients for
input clock of 24 MHz and so are registered only in this case. MPLL does
not need runtime reconfiguration and so table for it is not provided.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/samsung/clk-exynos4.c