[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew...
authorCraig Topper <craig.topper@sifive.com>
Fri, 23 Jul 2021 16:05:23 +0000 (09:05 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 23 Jul 2021 16:12:05 +0000 (09:12 -0700)
commit5edccc45815518046d715d384c168f41b578cd6c
treec3b498b8120a4ff4af3a0915c91a42109ec6ea19
parent1e4ba7eba607623cd12cddd459258ffcad15ee1b
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.

Since we're changing VTYPE, we may change VLMAX which could
invalidate the previous VL. If we can't tell if it is safe we
should use an AVL of 1 instead of keeping the old VL.

This is a quick fix. We may want to thread VL to the pseudo
instruction instead of making up a value. That will require ISD
opcode changes and changes to the C intrinsic interface.

This fixes the issue raised in D106286.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D106403
16 files changed:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll