[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Sat, 28 Apr 2018 18:14:50 +0000 (18:14 +0000)
commit5eb9f581b664e0e35c6bf6db4f696f57a8516523
tree86d78c764aeb7ba74eba499432bb8ae2b0a82605
parent2d2698c69cc852f33361094c998f0ddf0297355d
[globalisel][legalizerinfo] Introduce dedicated extending loads and add lowerings for them

Summary:
Previously, a extending load was represented at (G_*EXT (G_LOAD x)).
This had a few drawbacks:
* G_LOAD had to be legal for all sizes you could extend from, even if
  registers didn't naturally hold those sizes.
* All sizes you could extend from had to be allocatable just in case the
  extend went missing (e.g. by optimization).
* At minimum, G_*EXT and G_TRUNC had to be legal for these sizes. As we
  improve optimization of extends and truncates, this legality requirement
  would spread without considerable care w.r.t when certain combines were
  permitted.
* The SelectionDAG importer required some ugly and fragile pattern
  rewriting to translate patterns into this style.

This patch begins changing the representation to:
* (G_[SZ]EXTLOAD x)
* (G_LOAD x) any-extends when MMO.getSize() * 8 < ResultTy.getSizeInBits()
which resolves these issues by allowing targets to work entirely in their
native register sizes, and by having a more direct translation from
SelectionDAG patterns.

This patch introduces the new generic instructions and new variation on
G_LOAD and adds lowering for them to convert back to the existing
representations.

Depends on D45466

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, aemerson, javed.absar

Reviewed By: aemerson

Subscribers: aemerson, kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D45540

llvm-svn: 331115
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir [new file with mode: 0644]