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(parent: cb65e07) | patch
intel/compiler: move gen5 final pass to actually be final pass
authorDave Airlie <airlied@redhat.com>
Mon, 18 Dec 2023 06:47:56 +0000 (16:47 +1000)
committerEric Engestrom <eric@engestrom.ch>
Wed, 20 Dec 2023 00:04:51 +0000 (00:04 +0000)
commit5ea94d17248a91e3598306ada8085a7c144adb15
tree15c9bddce7b5cff6cfbd409c600bb09beb9fed56tree | snapshot
parentcb65e078a7c93e9cf8a1b549d9bf7f430b27681fcommit | diff
intel/compiler: move gen5 final pass to actually be final pass

This got broken by the register conversion, this pass needs to be
after all the others.

Fixes: ce75c3c3fea9 ("intel: Switch to intrinsic-based registers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
(cherry picked from commit f76f4be301ef311e6be21486b6a3f5fd5e90240f)
.pick_status.json diff | blob | history
src/intel/compiler/brw_nir.c diff | blob | history
Domain: Graphics System / GL;