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(parent: 316c83b) | patch
RISC-V: allow vx instruction use "zero" as scalar register.
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Tue, 7 Feb 2023 07:49:16 +0000 (15:49 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Sun, 12 Feb 2023 06:41:14 +0000 (14:41 +0800)
commit5e620b36cd34b85b0e28c34160245d84bc5acd68
tree21367addfd6d6325374266c1100e2380f86244ebtree | snapshot
parent316c83b158dbae2559f130fb7e44718c99941266commit | diff
RISC-V: allow vx instruction use "zero" as scalar register.

  li a5,0
  vdiv.vx v0,v1,a5 =======> vdiv.vx v0,v1,zero

gcc/ChangeLog:

* config/riscv/vector.md: use "zero" reg.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: New test.
gcc/config/riscv/vector.md diff | blob | history
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c [new file with mode: 0644] blob
Domain: System / Toolchain;