drm/rockchip: dw_hdmi: introduce the VPLL clock setting
authorMark Yao <mark.yao@rock-chips.com>
Fri, 9 Jun 2017 07:10:41 +0000 (15:10 +0800)
committerMark Yao <mark.yao@rock-chips.com>
Fri, 23 Jun 2017 00:52:03 +0000 (08:52 +0800)
commit5e3bc6d1ab48a20cbce3d59d42937bc977ec61cf
treefd9f992c12f98a8004540d3b1b529955fac96dcf
parent6445e394c54b61974491fccbf2e4fcd990d2fa8b
drm/rockchip: dw_hdmi: introduce the VPLL clock setting

For RK3399 HDMI, there is an external clock need for HDMI PHY,
and it should keep the same clock rate with VOP DCLK.

VPLL have supported the clock for HDMI PHY, but there is no
clock divider bewteen VPLL and HDMI PHY. So we need to set the
VPLL rate manually in HDMI driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c