projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ee85240) | patch
[AMDGPU] Enforce alignment of image vaddr on gfx90a
authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Wed, 18 May 2022 19:22:38 +0000 (12:22 -0700)
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Tue, 24 May 2022 17:05:39 +0000 (10:05 -0700)
commit5df6669d45bc72df8a9ac7fb0f4f4cfc00444e0d
tree3bc1cc6114890d824a9c717262a7ac32fe85eb9ctree | snapshot
parentee8524087c78a673fcf5486ded69ee597a85e0f1commit | diff
[AMDGPU] Enforce alignment of image vaddr on gfx90a

Even though single address image instructions only use a single VGPR
HW accesses 4 or 5 which creates alignment requirement.

Fixes: SWDEV-316648

Differential Revision: https://reviews.llvm.org/D126009
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp diff | blob | history
llvm/lib/Target/AMDGPU/MIMGInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.h diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.dim.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.gfx90a.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir [new file with mode: 0644] blob
Domain: System / Toolchain;