arm64: kernel: enforce pmuserenr_el0 initialization and restore
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 18 Dec 2015 10:35:54 +0000 (10:35 +0000)
committerSasha Levin <sasha.levin@oracle.com>
Mon, 1 Feb 2016 17:22:13 +0000 (12:22 -0500)
commit5de8e1eed3221cb8737c2617c4567b70833795e6
tree1c9ff445d7448f19839014e8a0f1d8cf1fb35700
parent1d4c425164b922424b3f86f93f3f0b7f85293fa7
arm64: kernel: enforce pmuserenr_el0 initialization and restore

[ Upstream commit d2d39a3b91628ef5abdf58e83905b173e63d5ecf ]

commit 60792ad349f3c6dc5735aafefe5dc9121c79e320 upstream.

The pmuserenr_el0 register value is architecturally UNKNOWN on reset.
Current kernel code resets that register value iff the core pmu device is
correctly probed in the kernel. On platforms with missing DT pmu nodes (or
disabled perf events in the kernel), the pmu is not probed, therefore the
pmuserenr_el0 register is not reset in the kernel, which means that its
value retains the reset value that is architecturally UNKNOWN (system
may run with eg pmuserenr_el0 == 0x1, which means that PMU counters access
is available at EL0, which must be disallowed).

This patch adds code that resets pmuserenr_el0 on cold boot and restores
it on core resume from shutdown, so that the pmuserenr_el0 setup is
always enforced in the kernel.

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
arch/arm64/kernel/perf_event.c
arch/arm64/mm/proc.S