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(parent: 905a7d0) | patch
drm/vc4: dsi: Correct max divider to 255 (not 7)
authorDave Stevenson <dave.stevenson@raspberrypi.com>
Fri, 22 Oct 2021 15:48:50 +0000 (16:48 +0100)
committerDom Cobley <popcornmix@gmail.com>
Mon, 21 Mar 2022 16:04:38 +0000 (16:04 +0000)
commit5d2bec3c00c4ee74eff5c890256de371e873568d
treef3faf49c6a9ab18050d0324d08746496d0203d52tree | snapshot
parent905a7d0b1efdc530c33507884439b1ad0a76c36ccommit | diff
drm/vc4: dsi: Correct max divider to 255 (not 7)

The integer divider from parent PLL to DSI clock is capable
of going up to /255, not just /7 that the driver was trying.
This allows for slower link frequencies on the DSI bus where
the resolution permits.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
drivers/gpu/drm/vc4/vc4_dsi.c diff | blob | history
Domain: System / Kernel;