[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32
authorDavid Green <david.green@arm.com>
Mon, 16 May 2022 17:00:30 +0000 (18:00 +0100)
committerDavid Green <david.green@arm.com>
Mon, 16 May 2022 17:00:30 +0000 (18:00 +0100)
commit5d29d752735e71b73a54bfc9ab747384be9e4246
treedab9082baa18e2e6f10ef1782454167a339bcd0d
parent3794cc0e996481e10307b67c8436aa44e0d65d22
[AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32

There have been some patterns in the AArch64 backend to optimize code of
the form:
  ldrsh w8, [x0]
  scvtf s0, w8
to:
  ldr h0, [x0]
  sshll v0.4s, v0.4h, #0
  scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.

This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.

Differential Revision: https://reviews.llvm.org/D125470
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-scvt.ll
llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll