[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.
authorCraig Topper <craig.topper@sifive.com>
Mon, 11 Jan 2021 02:01:23 +0000 (18:01 -0800)
committerCraig Topper <craig.topper@sifive.com>
Mon, 11 Jan 2021 03:15:45 +0000 (19:15 -0800)
commit5cf73dca77e52f54c893d2c5fc2f56a5f2764f7d
treec2c002174bf7c9c75d4d2d32ea75e3274be17b75
parent7539c75bb438f185575573ed4ea8da7cb37d3f2a
[RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.

This patch moves all but the BaseInstr to bits in TSFlags.

For the index fields, we can just use a bit to indicate their presence.
The locations of the operands are well defined.

This reduces the llc binary by about 32K on my build. It also
removes the binary search of the table from the custom inserter.
Instead we just check that the SEW op is present.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D94375
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h