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(parent: 4c421a2) | patch
AMDGPU: Lower buffer store and atomic intrinsics manually
authorMarek Olsak <marek.olsak@amd.com>
Thu, 9 Nov 2017 01:52:48 +0000 (01:52 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Thu, 9 Nov 2017 01:52:48 +0000 (01:52 +0000)
commit5cec64195ceea262f86ae3d305607eb4e7840d88
tree5d099f28db7c62a8b4d7d6977301f952ac46687atree | snapshot
parent4c421a2db26753e771ca3676053352516e55e2c7commit | diff
AMDGPU: Lower buffer store and atomic intrinsics manually

Summary:
Without this, SIMemoryLegalizer inserts s_waitcnt vmcnt(0) before every
buffer store and atomic instruction.

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D39060

llvm-svn: 317754
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h diff | blob | history
llvm/lib/Target/AMDGPU/BUFInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.td diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll diff | blob | history
Domain: System / Toolchain;