AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 27 Dec 2019 22:41:16 +0000 (17:41 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Fri, 27 Dec 2019 22:52:12 +0000 (17:52 -0500)
commit5ce2ca524e99189fb778d21f63ec0c78944383e5
treea20bcdd2b9603052442b469f1addcc0c2b8f841a
parente9775bb5d81a1eb1d73319877519e51ed3b9f865
AMDGPU/GlobalISel: Use SReg_32 for readfirstlane constraining

This matches the DAG behavior where we don't use SReg_32_XM0
everywhere anymore, and fixes not coalescing the copies into m0.
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir