projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 498d311) | patch
[x86, AVX] allow FP vector select folding to bitwise logic ops (PR28895)
authorSanjay Patel <spatel@rotateright.com>
Wed, 10 Aug 2016 19:00:11 +0000 (19:00 +0000)
committerSanjay Patel <spatel@rotateright.com>
Wed, 10 Aug 2016 19:00:11 +0000 (19:00 +0000)
commit5ccc85fe83500cd9c54dd4dfb5fd3cad761d4830
treea1ac251dfaa52b69483d7c8e8956f88050acbed4tree | snapshot
parent498d3113c35d8d4f80e4d79ac9b75c3980bfc8c3commit | diff
[x86, AVX] allow FP vector select folding to bitwise logic ops (PR28895)

This handles the case in:
https://llvm.org/bugs/show_bug.cgi?id=28895

...but we are not getting all of the possibilities yet.
Eg, we use 'X86::FANDN' for scalar FP select combines.

That enhancement is filed as:
https://llvm.org/bugs/show_bug.cgi?id=28925

Differential Revision: https://reviews.llvm.org/D23337

llvm-svn: 278270
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/avx512-cvt.ll diff | blob | history
llvm/test/CodeGen/X86/select-with-and-or.ll diff | blob | history
Domain: System / Toolchain;