ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate
authorLiu Ying <Ying.Liu@freescale.com>
Thu, 12 Feb 2015 06:01:29 +0000 (14:01 +0800)
committerShawn Guo <shawn.guo@linaro.org>
Mon, 2 Mar 2015 12:52:13 +0000 (20:52 +0800)
commit5ccc248cc53708337a2bfe4ea380c20948e8bbed
treed0c9d3d0bcd14fe588e50d756bd6095abadbc858
parent721fee59d26e46700476f4c70572e9e0f1cc8fd3
ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate

The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals.  This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output.  The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock.  In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.

Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/mach-imx/clk-imx6q.c
include/dt-bindings/clock/imx6qdl-clock.h