pinctrl: mvebu: armada-39x: align NAND pin naming
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 9 Jun 2015 16:47:07 +0000 (18:47 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 10 Jun 2015 09:11:39 +0000 (11:11 +0200)
commit5cc0de1faff6ac801286dfab88e4a31392cbb3f0
tree455542fe5a00446773556309453ed9fc466b171c
parent7bd6a26db6f9dade7dbd88a73120d17da1ee0e89
pinctrl: mvebu: armada-39x: align NAND pin naming

All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.

It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.

While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
drivers/pinctrl/mvebu/pinctrl-armada-39x.c