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(parent: 39f48fd) | patch
[X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.
authorCraig Topper <craig.topper@intel.com>
Fri, 7 Sep 2018 20:56:03 +0000 (20:56 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 7 Sep 2018 20:56:03 +0000 (20:56 +0000)
commit5cbce81c915d122d6eddea767206506ad3b2fb91
tree313a5b51e020eb902d39eb571acc2074975f56datree | snapshot
parent39f48fdcbc9d2603da80acbd65b50717d576c9b3commit | diff
[X86] Don't create ZERO_EXTEND_INREG/SIGN_EXTEND_INREG for v1iX vectors.

The generic type legalizer will scalarize vXi1 instructions getting rid of the vector entirely. Creating wider vector instructions is just going to prevent that.

llvm-svn: 341705
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/avg.ll diff | blob | history
llvm/test/CodeGen/X86/vec_cast.ll diff | blob | history
Domain: System / Toolchain;