intel/eu: Fix XeHP register region validation for hstride == 0

intel/eu: Fix XeHP register region validation for hstride == 0

Recently, we started using <1;1,0> register regions for consecutive
channels, rather than the <8;8,1> we've traditionally used, as the
<1;1,0> encoding can be compacted on XeHP.  Since then, one of the
EU validator rules has been flagging tons of instructions as errors:

   mov(16)   g114<1>F   g112<1,1,0>UD   { align1 1H I@2 compacted };
   ERROR: Register Regioning patterns where register data bit locations are changed between source and destination are not supported except for broadcast of a scalar.

Our code for this restriction checked three things:

   #1: vstride != width * hstride ||
   #2: src_stride != dst_stride ||
   #3: subreg != dst_subreg

Destination regions are always linear (no replicated values, nor
any overlapping components), as they only have hstride.  Rule #1 is
requiring that the source region be linear as well.  Rules #2-3 are
straightforward: the subregister must match (for the first channel to
line up), and the source/destination strides must match (for any
subsequent channels to line up).

Unfortunately, rules #1-2 weren't working when horizontal stride was 0.
In that case, regions are linear if width == 1, and the stride between
consecutive channels is given by vertical stride instead.

So we adjust our src_stride calculation from

   src_stride = hstride * type_size;

to:

   src_stride = (hstride ? hstride : vstride) * type_size;

and adjust rule #1 to allow hstride == 0 as long as width == 1.

While here, we also update the text of the rule to match the latest
documentation, which apparently clarifies that it's the location of
the LSB of the channel which matters.

Fixes: 3f50dde8b35 ("intel/eu: Teach EU validator about FP/DP pipeline regioning restrictions.")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17624>