vect: Don't split store groups if we have IFN_STORE_LANES [PR99873]

vect: Don't split store groups if we have IFN_STORE_LANES [PR99873]

As noted in the PR, we were no longer using ST3 for the testcase and
instead stored each lane individually.  This is because we'd split
the store group during SLP and couldn't recover when SLP failed.

However, we can also get better code with ST3 and ST4 even if SLP would
have succeeded, such as for vect-complex-5.c.  I'm not sure exactly
where the cut-off point is, but it seems reasonable to allow the split
if either of the new groups would operate on full vectors *within*
rather than across scalar loop iterations.

E.g. on a Cortex-A57, pr99873_3.c performs better using ST4 while
pr99873_2.c performs better with SLP.

Another factor is that SLP can handle smaller iteration counts than
IFN_STORE_LANES can, but we don't have the infrastructure to choose
reliably based on that.

gcc/
	PR tree-optimization/99873
	* tree-vect-slp.c (vect_slp_prefer_store_lanes_p): New function.
	(vect_build_slp_instance): Don't split store groups that could
	use IFN_STORE_LANES.

gcc/testsuite/
	* gcc.dg/vect/slp-21.c: Only expect 2 of the loops to use SLP
	if IFN_STORE_LANES is available.
	* gcc.dg/vect/vect-complex-5.c: Expect no loops to use SLP if
	IFN_STORE_LANES is available.
	* gcc.target/aarch64/pr99873_1.c: New test.
	* gcc.target/aarch64/pr99873_2.c: Likewise.
	* gcc.target/aarch64/pr99873_3.c: Likewise.
	* gcc.target/aarch64/sve/pr99873_1.c: Likewise.
	* gcc.target/aarch64/sve/pr99873_2.c: Likewise.
	* gcc.target/aarch64/sve/pr99873_3.c: Likewise.