clk: tl1: add clk81 mux clock [1/1]

clk: tl1: add clk81 mux clock [1/1]

PD#SWPL-8215

Problem:
1.clk81 can not switch to 24M
2.fixed pll can set rate
  call clk_prepare_enable to open it
  call clk_disable_unprepare to close it

Solution:
1.add clk81 mux clock
2.change fixed pll callback Read only to R/W

Verify:
test passed on tm2 ab301

Change-Id: I426d4307f19647afcb0166a23c1988df1b504807
Signed-off-by: Jian Hu <jian.hu@amlogic.com>