arm64: Fix the feature type for ID register fields
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Thu, 19 Oct 2017 15:39:02 +0000 (16:39 +0100)
committerWill Deacon <will.deacon@arm.com>
Thu, 19 Oct 2017 16:42:08 +0000 (17:42 +0100)
commit5bdecb7971572a1aef828df507558e7a4dfe25ec
treeaf046eaa94b6ad06047291a7c3f5ab277d183c98
parent3f7c86b2382ea721c4fe9a7532bf5dc1b414ec1a
arm64: Fix the feature type for ID register fields

Now that the ARM ARM clearly specifies the rules for inferring
the values of the ID register fields, fix the types of the
feature bits we have in the kernel.

As per ARM ARM DDI0487B.b, section D10.1.4 "Principles of the
ID scheme for fields in ID registers" lists the registers to
which the scheme applies along with the exceptions.

This patch changes the relevant feature bits from FTR_EXACT
to FTR_LOWER_SAFE to select the safer value. This will enable
an older kernel running on a new CPU detect the safer option
rather than completely disabling the feature.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dave Martin <dave.martin@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/kernel/cpufeature.c