[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Wed, 15 Aug 2018 15:30:36 +0000 (15:30 +0000)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Wed, 15 Aug 2018 15:30:36 +0000 (15:30 +0000)
commit5b9a4f8ee5d17870c4e0077aa00329b387b5944a
treec1781eebaae5402f385b6a17b3e0ed2c1b328980
parent2a119b9a9849ae692da8b643ba8cfefd3b95ec73
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type

To make ISD::VSELECT available(legal) so long as there are altivec instruction,
otherwise it's default behavior is expanding.
Use xxsel to match vselect if vsx is open, or use vsel.

In order to do not write many patterns in td file, promote (for vector it's
bitcast) all other type into v4i32 and only pattern match vselect of v4i32 into
vsel or xxsel.

Patch by wuzish
Differential revision: https://reviews.llvm.org/D49531

llvm-svn: 339779
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/vec_select.ll