[RISCV] Set Fast flag for unaligned memory accesses
authorLuke Lau <luke@igalia.com>
Mon, 24 Jul 2023 09:58:22 +0000 (10:58 +0100)
committerLuke Lau <luke@igalia.com>
Mon, 24 Jul 2023 09:58:57 +0000 (10:58 +0100)
commit5b95bba6fe411e82c7c31cb542748b00ff633cdb
tree4322ab5f08939250c1126f702888dd7d89b03caf
parent587b8f323d2db30928a2d9f54412aeead69b6cb7
[RISCV] Set Fast flag for unaligned memory accesses

The +unaligned-scalar-mem and +unaligned-vector-mem features were added in
D126085 and D149375 respectively to allow subtargets to indicate that
they supported misaligned loads/stores with "sufficient" performance.
This is separate from whether or not the target actually supports
misaligned accesses, which could be determined from Zicclsm.

This patch enables the Fast flag under the assumption that any subtarget
that declares support for +unaligned-*-mem will want to opt into
optimisations that take advantage of misaligned scalar accesses, such as
store merging.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D150771
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/memcpy-inline.ll
llvm/test/CodeGen/RISCV/memset-inline.ll
llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
llvm/test/CodeGen/RISCV/unaligned-load-store.ll