author | Qingqing Zhuo <qingqing.zhuo@amd.com> | |
Thu, 27 Jan 2022 02:52:11 +0000 (21:52 -0500) | ||
committer | Alex Deucher <alexander.deucher@amd.com> | |
Fri, 18 Feb 2022 19:07:00 +0000 (14:07 -0500) | ||
commit | 5b723b12301272ed3c6c99c4ad8b43a520f880ea | |
tree | 4fe7d279c7b95c8dfda54a5dcba8cd70ac34608c | tree | snapshot |
parent | 62640f251f4777cbed654e59827fccd3b4c94bce | commit | diff |
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h | [new file with mode: 0644] | blob |
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h | [new file with mode: 0644] | blob |
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_offset.h | [new file with mode: 0644] | blob |
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_sh_mask.h | [new file with mode: 0644] | blob |